说明

CD40110B is a dual-clocked up/down counter with a special preconditioning circuit that allows the counter to be clocked, via positive going inputs, up or down regardless of the state or timing (within 100 ns typ.) of the other clock line.

The clock signal is fed into the control logic and Johnson counter after it is preconditioned. The outputs of the Johnson counter (which include anti-lock gating to avoid being locked at an illegal state) are fed into a latch. This data can be fed directly to the decoder through the latch or can be strobed to hold a particular count while the Johnson counter continues to be clocked. The decoder feeds a seven-segment bipolar output driver which can source up to 25 mA to drive LEDs and other displays such as low-voltage fluorescent and incandescent lamps.

View full Description in Datasheet

特性

• Separate clock-up and clock-down lines
• Capable of driving common cathode LEDs and other displays directly
• Allows cascading without any external circuitry
• 100% tested for quiescent current at 20 V
• Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
• Noise margin (full package-temperature range) =
  1 V at V_DD = 5 V
  2 V at V_DD = 10 V
  2.5 V at V_DD = 15 V
• 5 V, 10 V and 15 V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices".
• Applications
  • Rate comparators
  • General counting applications where display is desired
  • Up-down counting applications where input pulses are random in nature